1. Field of the Invention
The present invention relates to a circuit for receiving bits transmitted asynchronously, and more specifically to a reception error detection circuit.
2. Discussion of the Related Art
FIG. 1 schematically shows a circuit for receiving bits transmitted on an asynchronous signal Din. Signal Din is provided to a phase-locked loop (PLL) 10 to reconstruct a clock signal CKR, the period of which is in principle equal to the width of the bits of signal Din. Reconstructed clock CKR is used to sample asynchronous signal Din by means of a flip-flop 12 that provides the sampled bits on a synchronous signal Ds. Ideally, signal CKR is such that flip-flop 12 samples each bit of asynchronous signal Din at its center.
The accuracy of reconstructed clock CKR depends on several factors, especially on the regularity of the variation of asynchronous signal Din. Asynchronous signal Din is random, but it can often convey several consecutive bits at a same state, which causes a drift of phase-locked loop 10 towards a lower frequency. Further, parasitic pulses in asynchronous signal Din are likely to cause a drift of phase-locked loop 10 towards a higher frequency.
When the frequency of reconstructed clock CKR is not exactly set on the transmission rate of asynchronous signal Din, the circuit inevitably ends up making sampling errors.
FIG. 2 shows an example of a timing diagram of the signals of the circuit in FIG. 1, illustrating an error occurring when the frequency of reconstructed clock CKR is higher than the transmission rate of the bits on signal Din. For simplification, the signals have been shown in square form. In reality, these signals have smooth transitions. The switching and propagation delays of the flip-flops have also been neglected.
In this example, the successive bits transmitted on signal Din switch at each bit, and signal Din is sampled upon each rising edge of clock signal CKR.
Upon the first rising edge of clock CKR, a bit of signal Din, at 1, is sampled in ideal conditions, that is, substantially at its center. Signal Ds switches to 1 during this rising edge.
At a given time, two successive rising edges of clock CKR, here the fourth and fifth rising edges, occur within a same bit of signal Din. In other words, the same bit is sampled twice, which causes an error. In the example of FIG. 2, synchronous signal Ds conveys, at the time of occurrence of the error, two successive bits at 0.
When clock CKR is too slow, at a given time, two of its successive rising edges occur before and after a bit of signal Din, which causes the loss of this bit.
A conventional solution to detect errors in such a system is to compare the control signal of the oscillator of phase-locked loop 10 with high and low thresholds substantially equidistant from the nominal value of the control signal. When the control signal reaches one of these thresholds, this means that the phase-locked loop has drifted, and thus that the reconstructed clock is wrong. The thresholds must be sufficiently far apart from the nominal value so that they are not reached by variations of the control signal around the nominal value, due to noise and to manufacturing tolerances. Thus, the error detection reacts particularly slowly and, when it reacts, a significant unknown number of bits are erroneous.